2D Materials Beyond Graphene: The Transistor Revolution That Could Save Moore's Law

The Thickness Problem

Silicon has carried the semiconductor industry for six decades. Through relentless engineering — strained channels, high-k dielectrics, FinFETs, gate-all-around nanosheets — chipmakers have shrunk transistors from microns to single-digit nanometers. But physics is closing in. When a silicon channel thins below about 5 nanometers, quantum confinement degrades carrier mobility, surface roughness scattering dominates, and the transistor stops behaving like a transistor. Short-channel effects — the leakage currents and threshold voltage shifts that plague ultra-scaled devices — become unmanageable.

This isn’t a speculative concern. It’s the reason TSMC, Intel, Samsung, and IBM are all, independently, investigating the same class of replacement materials: transition metal dichalcogenides, or TMDs.

TMDs are layered compounds with the formula MX₂, where M is a transition metal (typically molybdenum or tungsten) and X is a chalcogen (sulfur, selenium, or tellurium). In their bulk form, they’ve been known to materials scientists for over a century — MoS₂ has been used as an industrial lubricant since the 1940s. What changed everything was a demonstration in 2011 that you could peel a single molecular layer off one of these crystals and make it work as a transistor channel.

That demonstration, published in Nature Nanotechnology by Radisavljevic et al., showed a single-layer MoS₂ field-effect transistor with a room-temperature on/off current ratio exceeding 10⁸ and electron mobility of approximately 200 cm²/V·s. The device was crude by industrial standards — mechanically exfoliated, with a back-gate geometry no fab would ever use. But it proved the concept that would launch a thousand research programs: an atomically thin semiconductor, just 0.65 nanometers thick, with a technologically useful bandgap, could switch current on and off with extraordinary electrostatic control.

Fifteen years later, TMDs are no longer a curiosity. They are the consensus answer to a question the semiconductor industry can no longer avoid: what comes after silicon channels?

Why TMDs, and Why Not Graphene?

Graphene was the first 2D material to capture the world’s attention, earning Andre Geim and Konstantin Novoselov the 2010 Nobel Prize in Physics. But graphene has a fatal flaw for digital electronics: no bandgap. A graphene transistor cannot fully turn off. No amount of engineering has solved this fundamental limitation for logic applications.

TMDs sidestep this problem entirely. Monolayer MoS₂ has a direct bandgap of approximately 1.8 eV — larger than silicon’s 1.12 eV. This wide bandgap means extremely low off-state leakage, which translates directly to lower standby power in chips. Other members of the family offer a spectrum of bandgaps: WS₂ at roughly 2.0 eV, WSe₂ at 1.65 eV, MoSe₂ at 1.55 eV. Designers could, in principle, select the optimal material for each application — wide-gap TMDs for low-power logic, narrower-gap variants for high-speed analog circuits.

But the real advantage isn’t the bandgap — it’s the thickness. A monolayer TMD channel is three atoms thick: one plane of metal atoms sandwiched between two planes of chalcogen atoms. This extreme thinness gives the gate electrode nearly perfect electrostatic control over the channel. In transistor physics, this is quantified by a parameter called the “natural length” — the distance over which the source and drain electric fields penetrate into the channel. For a 0.65 nm MoS₂ monolayer, this natural length is far shorter than for any achievable silicon channel, meaning TMD transistors can theoretically scale to shorter gate lengths before short-channel effects become problematic.

This is the core proposition: not that TMDs are better than silicon in every metric, but that they can keep scaling where silicon cannot.

The Material Zoo: Properties That Matter

The semiconducting TMDs relevant to transistor applications share a common crystal structure — the 2H polytype, where each layer has trigonal prismatic coordination — but differ significantly in their electronic properties. Here’s what matters for device engineers:

MoS₂ remains the most studied TMD. Its monolayer bandgap of ~1.8 eV (direct) drops to ~1.29 eV (indirect) in bulk form. Room-temperature electron mobility in practical devices ranges from 50–200 cm²/V·s, depending heavily on the dielectric environment, substrate quality, and contact resistance. Theoretical calculations predict intrinsic phonon-limited mobility around 400 cm²/V·s — a ceiling that researchers are still working to approach.

WSe₂ is the most promising candidate for p-type (hole-conducting) transistors. It exhibits ambipolar transport, meaning it can conduct both electrons and holes, with hole mobility values of 100–200 cm²/V·s reported in high-quality samples. This ambipolarity is valuable: building complementary logic circuits (CMOS) requires both n-type and p-type transistors. WSe₂ could potentially serve double duty, or pair with MoS₂ in a complementary scheme.

WS₂ offers the widest bandgap (~2.0 eV) among the commonly studied TMDs, making it attractive for ultra-low-power applications. It also exhibits somewhat better oxidation resistance than MoS₂, a practical consideration for fabrication processes that expose channel surfaces to ambient conditions.

MoSe₂ and MoTe₂ sit at the lower end of the bandgap spectrum (~1.55 eV and ~1.0 eV respectively), offering lower threshold voltages at the expense of higher leakage current.

A critical caveat: these mobility values are substantially lower than bulk silicon’s ~1,400 cm²/V·s for electrons. TMD advocates argue — with justification — that the comparison is misleading. When silicon is thinned to comparable dimensions (sub-5 nm), its effective mobility collapses due to surface roughness and quantum confinement. The relevant comparison is between a TMD monolayer and an ultra-thin silicon body, and there the TMD can win.

The Dielectric Environment: It’s Not Just the Channel

One of the key insights of the past decade is that TMD device performance depends as much on what surrounds the channel as on the channel itself. The atomically thin nature of TMDs means that charge traps at interfaces, remote phonon scattering from substrates, and trapped impurities all have outsized effects on mobility.

Hexagonal boron nitride (h-BN) encapsulation — sandwiching the TMD between atomically flat h-BN layers — has become the gold standard in research labs. This approach reduces interface trap density by one to two orders of magnitude and can triple field-effect mobility. Researchers at institutions including Columbia University and the National University of Singapore (NUS) have demonstrated that h-BN encapsulated MoS₂ devices approach the intrinsic phonon-limited mobility.

The problem: h-BN encapsulation is currently incompatible with high-volume manufacturing. Growing device-quality h-BN at wafer scale is itself a major challenge, and the transfer and alignment processes add cost and complexity. For production, the industry will likely need to develop CMOS-compatible alternatives — high-quality ALD-deposited Al₂O₃ or HfO₂ dielectrics with engineered interfaces. IMEC’s 2D materials program has made this a central focus, exploring passivation strategies that can reduce interface trap density without requiring h-BN.

The Manufacturing Gauntlet

Laboratory demonstrations of TMD transistors now routinely show impressive metrics — subthreshold swings near the thermionic limit of 60 mV/decade, on/off ratios above 10⁸, and respectable current densities. The challenge has shifted from “can we make a good device?” to “can we make billions of them?”

This manufacturing challenge breaks down into three interlinked problems.

Growing Perfect Crystals at Wafer Scale

The primary industrial pathway to TMD thin films is chemical vapor deposition (CVD), using metal-organic precursors like Mo(CO)₆ or W(CO)₆ with chalcogen sources such as H₂S. On optimized substrates — typically c-plane sapphire — CVD can produce continuous MoS₂ films with grain sizes up to 100 micrometers and crystal misorientation below 5 degrees.

But “optimized substrates” is doing a lot of work in that sentence. Achieving uniform monolayer coverage across an entire 300mm wafer requires extraordinary control over temperature (±0.5°C uniformity), precursor delivery, and nucleation density. TSMC has been actively researching 2D material integration for sub-2nm technology nodes, and their published work highlights the gap between laboratory-scale and production-scale CVD. Thickness variations of even a single atomic layer can shift the bandgap by hundreds of millielectronvolts, creating unacceptable device-to-device variation.

Metal-organic chemical vapor deposition (MOCVD) is emerging as the most promising production technique, offering better precursor control than conventional CVD. But MOCVD tools optimized for TMDs remain expensive — estimates suggest 3–5× the cost of equivalent silicon epitaxy equipment — and throughput is low compared to the silicon ecosystem’s mature processes.

The Contact Resistance Crisis

If CVD growth is the first mountain, contact resistance is the second — and arguably the steeper one. When a metal electrode contacts a TMD, the interface typically forms a Schottky barrier rather than an ohmic contact. This barrier, ranging from 0.1 to 0.5 eV depending on the metal and TMD, chokes current flow and dominates the total device resistance, particularly in short-channel transistors where the channel resistance itself is small.

The fundamental issue is Fermi-level pinning: metal-induced gap states at the metal-TMD interface pin the Fermi level near mid-gap, regardless of the metal’s work function. Traditional contact engineering tricks from silicon technology — heavy doping under contacts, silicide formation — don’t translate to 2D materials.

Researchers have pursued several creative solutions. Phase engineering converts the semiconducting 2H phase of MoS₂ to the metallic 1T’ phase at contact regions, creating a lateral metal-semiconductor junction within the same material. Bismuth contacts, first demonstrated by researchers in China, exploit a unique orbital interaction that avoids Fermi-level pinning and have achieved contact resistances below 150 Ω·μm. Transferred metal contacts — where metals are deposited on a separate substrate and then laminated onto the TMD — can produce near-ideal interfaces but are impractical for manufacturing.

IMEC has explored alloy contact strategies and edge-contact geometries, where the metal touches the exposed edges of the TMD layers rather than the top surface. Edge contacts offer lower resistance in principle, because they access the conductive d-orbitals of the transition metal atoms directly, but they add significant fabrication complexity.

The International Roadmap for Devices and Systems (IRDS) identifies contact resistance below 100 Ω·μm as a requirement for competitive TMD transistors. Several lab demonstrations have met this target; none have done so at wafer scale with production-compatible processes.

Gate Stack Integration

The final piece of the integration puzzle is the gate dielectric. TMDs present a fundamentally different surface chemistry than silicon: there are no dangling bonds on the basal plane of a pristine TMD, which is both a blessing (no native oxide to contend with) and a curse (atomic layer deposition nucleation is difficult on an inert surface).

Standard ALD processes for high-k dielectrics like HfO₂ and Al₂O₃ require surface functional groups to initiate growth. On TMDs, this typically means either a seed layer (evaporated metal oxide, plasma treatment, or molecular seeding) or modified ALD chemistry. Each approach introduces trade-offs: plasma treatments can damage the TMD, seed layers may increase interface trap density, and modified precursors may not achieve the same film quality.

Intel’s published research has explored ozone-based surface functionalization during Al₂O₃ ALD on MoS₂, demonstrating reduced interface trap density compared to conventional thermal ALD. But achieving the interface quality standard in silicon CMOS — Dit below 10¹⁰ cm⁻² eV⁻¹ — remains elusive for any TMD gate stack process.

Where the Industry Actually Stands

It’s important to separate what has been demonstrated from what has been promised. Here’s an honest assessment:

What’s real: Single-device demonstrations showing competitive performance metrics. TSMC, Intel, Samsung, and IMEC all have active 2D materials research programs. IBM has demonstrated MoS₂ transistors at IEDM conferences. Academic groups worldwide have produced thousands of papers refining growth, contacts, and device architectures.

What’s not yet real: Wafer-scale TMD transistor integration with yields and variability matching silicon CMOS. A complete TMD CMOS process (requiring both high-quality n-type and p-type transistors on the same substrate). EDA tools and compact models mature enough for circuit design. Reliability data showing TMD transistors meeting the 10-year operating lifetime required for commercial products.

The most likely near-term commercial applications aren’t in replacing silicon for cutting-edge logic. They’re in back-end-of-line (BEOL) integration — building TMD transistors in the metal interconnect layers above conventional silicon transistors. Because TMD CVD can be performed at relatively low temperatures (as low as 350°C in some processes), it’s compatible with back-end processing. This could enable monolithic 3D integration: silicon logic on the bottom, TMD-based memory selectors, analog circuits, or sensor elements stacked above.

TSMC’s research has explored this BEOL pathway as a pragmatic near-term application of 2D materials, distinct from the longer-term ambition of TMD-channel logic transistors competing directly with silicon at the front end.

The Bigger Picture: What’s at Stake

The semiconductor industry’s interest in TMDs isn’t driven by academic curiosity. It’s driven by economics and physics — specifically, the $700 billion global semiconductor market’s dependence on continued transistor scaling, and the physical reality that silicon scaling is approaching exhaustion.

If TMDs work — if the growth, contact, and integration challenges are solved at manufacturing scale — they could extend transistor scaling by several technology generations, perhaps a decade or more of continued improvement in transistor density and energy efficiency. For AI workloads, which are increasingly constrained by chip power consumption rather than raw transistor count, even modest improvements in transistor leakage current could be transformative.

If they don’t work, the industry faces a more fragmented future: continued silicon optimization with diminishing returns, supplemented by architectural innovations (chiplets, 3D stacking, novel compute paradigms) rather than fundamental transistor improvement.

The honest assessment is that TMDs are somewhere between five and fifteen years from volume production for logic applications, depending on which problems prove hardest to solve. The contact resistance challenge, in particular, remains stubbornly difficult. But the breadth of industrial investment — multiple leading-edge fabs pursuing parallel research tracks — suggests that the bet is being taken seriously.

What to Watch

For those following this space, here are the signposts that will indicate whether TMDs are on track:

Contact resistance at scale: When a major fab demonstrates sub-100 Ω·μm contacts across a full 300mm wafer with production-compatible metals, the commercialization timeline will accelerate dramatically.

BEOL demonstration chips: The first functional circuits built with TMD transistors in back-end layers above silicon logic will likely come from TSMC or IMEC within the next few years. These won’t be commercial products, but they’ll prove manufacturing feasibility.

CMOS pairing: A convincing demonstration of complementary n-type (likely MoS₂) and p-type (likely WSe₂) TMD transistors integrated on the same substrate with matched performance will be a watershed moment.

Reliability data: The unsexy but essential milestone — TMD transistors passing standard qualification tests (HTOL, NBTI, TDDB) at operating conditions representative of commercial use.

The story of TMDs and transistors is, fundamentally, the story of whether humanity can continue building better computers by making better switches. It’s a materials science problem, a manufacturing problem, and an engineering problem, all wrapped into one. The physics says it should work. The engineering isn’t there yet. The next decade will determine which of those statements wins out.

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