Intel

Researchers work in a state-of-the-art photolithography cleanroom at the London Centre for Nanotechnology. The extreme precision required for modern semiconductor manufacturing demands contamination-free environments where even a single dust particle can destroy thousands of transistors. Credit: Wikimedia Commons

ASML's 0.55 NA Revolution: The $400M Machines Enabling 2nm Chips

ASML’s High-NA EUV systems achieve 0.55 numerical aperture—double the resolution of current tools—enabling critical dimensions below 10 nanometers for the first time. These $400 million machines represent the most complex manufacturing equipment ever built, with mirror precision approaching the theoretical limits of physics. Intel received the first production system in December 2023, marking the beginning of true 2nm manufacturing capability that could deliver 50% performance gains in next-generation AI processors.

Backside Power Delivery Networks Revolutionize Sub-2nm Semiconductor Manufacturing

TSMC leads mass production of 2nm nodes with backside power delivery networks (BSPDN) in 2026, while Intel and Samsung develop competing architectures. This breakthrough technology places power rails on the wafer’s backside, reducing IR drop by up to 30% and enabling higher transistor densities for next-generation AI and HPC chips.

Backside Power Delivery Network Architecture

Backside Power Delivery Networks: Engineering the Power Grid Revolution at Sub-2nm Nodes

Major foundries are implementing backside power delivery networks to overcome IR drop limitations at advanced nodes. TSMC’s N2 (2025), Intel’s 18A PowerVia (2024), and Samsung’s SF2Z processes represent a fundamental shift from shared front-side routing to decoupled power architectures, addressing power delivery impedance that scales as ρL/A in increasingly constrained geometries.